Available for opportunities

Gandla Venga
Naveen

// Design Verification Engineer · VLSI

SystemVerilog & UVM specialist focused on RTL functional verification, constrained-random testbench development, and CDC-aware verification methodologies. Passionate about achieving silicon-ready coverage closure.

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97%
Functional Coverage
100%
Code Coverage
3+
UVM Projects
AMBA
Protocol Verified
Gandla Venga Naveen
VLSI DV Engineer · Bengaluru
01

Technical Skills

⚡
HDL & Programming
SystemVerilogVerilogPythonC
🧪
Verification Methodology
UVMConstrained RandomFunctional CoverageCode CoverageScoreboardingSVA
🔗
Protocols
AMBA APBAHBAXI
🕐
Design & Timing
CDCSTASetup/HoldSlack AnalysisMetastabilityFSM Design
🛠️
Tools & EDA
QuestaSimModelSimXilinx VivadoMATLABLinux (Ubuntu)
🏗️
Testbench Architecture
AgentDriverMonitorSequencerEnvironmentScoreboard
02

Verification Projects

// UVM · AMBA APB · SystemVerilog
AMBA APB RAM — UVM Based Functional Verification
  • Architected a full layered UVM testbench: Agent, Driver, Monitor, Sequencer, Environment, and Scoreboard
  • Implemented constrained-random sequences to verify read/write transactions and protocol compliance
  • Designed functional coverage model covering address range, control signals, and error scenarios
  • Built reference memory model for end-to-end data integrity checking
  • Verified PSLVERR behavior and PREADY handshake timing per AMBA APB specification
  • Performed waveform-based debugging to resolve protocol violations and FSM transition issues
Functional Coverage
97%
Code Coverage
100%
FLAGSHIP PROJECT
// CDC · Dual-Clock Domain · Gray Code
Asynchronous FIFO — CDC Focused RTL Verification
  • Verified dual-clock FIFO operating across independent read and write clock domains
  • Validated Gray-coded pointer synchronization across asynchronous clock boundaries
  • Ensured correct integration of 2-FF synchronizers to mitigate metastability risks
  • Verified full/empty flag behavior across different clock frequency ratios
  • Tested overflow, underflow, and reset recovery corner cases
CDC DESIGN
// Directed Testing · RTL · Corner Case
32-bit ALU — Functional Verification
  • Developed directed testbench covering arithmetic, logical, and shift operations
  • Verified carry-out, zero flag functionality, and boundary corner-case conditions
RTL VERIFIED
// Deep Learning · MIMO-OFDM · MATLAB · Python  |  Sep 2024 – Jan 2025
Channel Estimation of MIMO-OFDM Using Deep Learning
  • Implemented deep learning-based channel estimation for MIMO-OFDM targeting improved BER and throughput
  • Designed and optimized neural network models to reduce channel estimation error
  • Compared performance against Least Squares (LS) and MMSE estimators using MATLAB simulations
  • Analyzed estimation accuracy, error metrics, and system-level performance trade-offs
FINAL YEAR
// RTL Design · APB · FSM
RTL Design Experience
  • Designed synthesizable APB-compliant RAM using a 4-state FSM (IDLE → SETUP → ACCESS → TRANSFER)
  • Developed parameterized RTL modules following synthesizable coding guidelines
RTL DESIGN

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03

Education & Training

2021 – 2025
B.E. — Electronics & Communication Engineering
AMC Engineering College, Bengaluru
CGPA: 7.8 / 10
2025 – 2026
VLSI Design and Verification Program
Specialized Training · Bengaluru
Ongoing

Let's build silicon
together.

Open to VLSI Design Verification roles. Let's connect!

gvenganaveen@gmail.com +91 9172742345 LinkedIn GitHub